The fabrication and implementation of electronic circuits in IC chips can make use of CMOS processes to fabricate transistors. Such transistors include a gate stack having a gate dielectric layer. Commonly such gate dielectric layers are formed of materials such as silicon dioxide and its derivatives (such as silicon oxynitride). The usefulness of such gate dielectric materials is decreasing for some implementations.
Future generations of CMOS transistors will make increasing use of high-K dielectrics. Such high-K dielectrics offer several advantages. For example, as the size of transistors shrink and their operating voltages are reduced, the thickness of the gate dielectrics (e.g., SiO2 or its derivatives) are reduced accordingly. However, high leakage currents, inevitably result from this thinning dielectric layer. When applied to so-called 65 nm technologies these leakage currents begin to reach unacceptably high levels. For example, in 65 nm technologies, leakage currents on the order of 1-102 A (amps)/cm2 or greater can result using SiO2 or its derivatives in transistor gate dielectric layers. Replacing the SiO2-based dielectrics with high-K dielectrics will enable the physical thickness of the dielectrics to be increased while maintaining a relatively stable gate capacitance. Thus, high-K dielectrics are seen as a potential solution to some of the present gate leakage current problems.
Presently, the thickness of the SiO2-based dielectric gate layers has reached about 12-13 Å in the transistors of 65 nm technology node. Moreover, associated leakage currents have been shown to increase by an order of magnitude for each dielectric layer thickness reduction of 2 Å, which is close to the atomic size of either oxygen or silicon. Thus, the absence of only 1 or 2 atoms seriously increases the possibility of forming local current leakage paths. This raises serious issues concerning the repeatability of dielectric layer fabrication. By using high-K dielectrics this problem can be ameliorated by using thicker dielectric layers. Additionally, the need for extremely thin SiO2-based dielectric layers has highlighted serious reliability issues concerning the metrology techniques used to ensure the in-line control capability of fabrication facilities and techniques. By using thicker high-K dielectrics some of these reliability issues and metrology issues can be addressed.
Although the industry is beginning to acknowledge that high K dielectrics may prove useful, there is no industry-wide conclusion as which material is the best choice for CMOS applications. However, there are some similarities between many classes of high K dielectric materials. In general, crystalline materials can be used to form films with in higher K values, which is desirable, but detrimentally, these crystalline dielectric materials are also typically characterized by higher leakage currents, a situation which defeats the purpose of using high-K dielectrics.
Present processes for fabricating such high-K dielectric layers presents some problems which have not yet been successfully addressed in the industry. As stated above, there is a need for process methods and high-K dielectric films capable of reliable and repeatable fabrication for use in integrated circuits.